1. Field of the Invention
The present invention relates to a semiconductor memory having ferroelectric capacitors. Particularly, this invention relates to non-volatile semiconductor memories having ferroelectric capacitors in high density and methods of fabricating such non-volatile semiconductor memories.
2. Discussion of the Background
A memory which includes series connected memory cells each having a transistor with a source terminal and a drain terminal and a ferroelectric capacitor in between the two terminals (hereinafter named “Series connected TC unit type ferroelectric RAM”) have been developed for highly reliable non-volatile semiconductor memories with low power consumption and high density.
Such non-volatile semiconductor memories are described in FIG. 34. The feature of this type of memory is a memory cell including one transistor and one capacitor, and a plurality of memory cells are connected in series. Namely, a lower electrode of a capacitor of the memory cell is connected to one of the source-drain regions formed adjacent to a gate, and an upper electrode of a capacitor of the memory cell is connected to the other of the source-drain regions.
In this structure, one block of memory cells usually includes eight bits unit cells or 16 bits unit cells. Each block is electrically disconnected in consideration of an increase of the capacitance of bit lines or resistance of performing a switching operation on switching transistors. One block of memory cells is usually disconnected by block selecting transistors. Further, it is necessary to arrange a plate line which drives a capacitor electrode in an opposite direction of a capacitor connected to the bit lines on the opposite direction in one block. Such a feature is disclosed in the “JSSCC, pp 787–792, May, 1998, D. Takashima et al.” and U.S. Pat. No. 5,903,492, the entire contents of these references being incorporated herein by reference.
The conventional semiconductor device having the ferroelectric capacitors in the “Series connected TC unit type ferroelectric RAM” is described with respect to FIGS. 35–40. In FIG. 35, an upper side of the conventional semiconductor device of the block selector portion is shown. In this drawing, there are two block selectors and two memory cell blocks on regions arranged on two parallel lines. FIG. 36 illustrates a sectional drawing as the line “S-T” of FIG. 35.
A block selecting transistor includes a first gate 100, a first impurity-diffused region 101, and a second impurity-diffused region 102 formed on a semiconductor substrate 103. A first bit line contact wire 104 is connected to the first impurity-diffused region 101 and a first metal wire contact 105 is connected to the first bit line contact wire 104. A second bit line contact wire 106 is connected to the first metal wire contact 105, and a bit line 107 is connected to the second bit line contact wire 106.
Further, a first cell transistor includes the second impurity-diffused region 102, a second gate 108 and a third impurity-diffused region 109 formed on the semiconductor substrate 103 and adjoined to the block selecting transistor.
In addition, a first capacitor includes a first lower electrode 110, a first ferroelectric layer 112 and a first upper electrode 113 formed over the second-impurity diffused region 102 and the second gate 108. The first lower electrode 110 is connected to the second-impurity diffused region 102 by a polysilicon plug 114.
A contact plug 115 is connected to the third impurity-diffused region 109. A first metal wiring 116 is connected to the contact plug 115, and a first metal contact 117 is formed and connected between the first upper electrode 113 and the first metal wiring 116.
Note a first memory cell includes the first cell transistor and the first capacitor. A second cell transistor includes the third impurity-diffused region 109, a third gate 118 and a fourth impurity-diffused region 119. A second capacitor includes a second lower electrode 450 formed over the third gate 118 and the fourth impurity-diffused region 119. The second ferroelectric layer 120 is formed on the second lower electrode 450, and a second upper electrode 121 is formed on the second ferroelectric layer 120. The second lower electrode 450 is connected to the fourth impurity-diffused region 119 by a second polysilicon plug 122. Further, a second metal contact 123 is formed and connected between the second upper electrode 121 and the first metal wiring 116.
Note a second memory cell includes the second cell transistor and the second capacitor. In addition, as shown, an isolation region 124 is formed on the semiconductor substrate 103 adjacent to the first impurity-diffused region 101.
Because of a micro loading effect, the cross sectional shape of the first upper electrode 113 may be damaged or changed in comparison with the second upper electrode 121. In more detail, the micro loading effect is caused by the difference of the distance between upper electrodes. Particularly, the length between the first upper electrode and another upper electrode is longer than the length between the first upper electrode and the second upper electrode.
In the memory cell, there are cyclical patterns of each memory capacitor, so there is the same length between each upper electrode in the memory cell area in each block. In a similar way, the lower electrodes are easily affected by the micro loading effect and the sectional shape thereof is easily varied in a neighbor of the block selecting transistor.
The micro loading effect is a significant physical phenomenon for the 0.3 micrometer scale. This effect is caused by a resist shape shrink because of over-etching of the resist at the specific point of an inperiodically portion, which is a different scale from the other portion.
Namely, while the etching step is performed, the etching speed of the non-periodical portion of the upper electrode is varied from the other upper electrode of the periodically portion. Thus, the edge portion of the resist for the upper electrode of the inperiodically portion may be varied from a predetermined shape. Further, in the end portion of the memory block, there is a relatively wide opening of the resist for the upper electrode. Therefore, the desired shape of resist of the portion in the end portion of the memory block is hardly acquired, in comparison with the other portion of the memory block, which have memory cells at even intervals.
Further, two memory blocks are facing each other by positioning two block selecting transistors between them. At the end portion of the memory blocks, the distance between upper electrodes in the end portions in each neighboring memory block is equal to the length of the two block selecting transistors and is 1.5 times the distance between two upper electrodes in a normal capacitor portion of the memory block. Therefore, the upper electrode of the end portion is reduced 70–90 percent compared to other normal upper electrodes.
In more detail, the step of forming a conventional upper electrode is shown in FIGS. 40(A) and 40(B). In FIG. 40(A), an overview of the resist pattern as the desired shape disposed on the upper electrode is shown. As shown, two resists 190, 191 facing a block selecting transistor are largely isolated a length of “L” greater than the interval length “M” of other resists 192, 193.
In FIG. 40(B), the cross sectional view on the line of “Y-Z” of the FIG. 40(A) is shown. In this figure, an upper electrode material 196 is provided on the ferroelectric layer 195. Also shown are the resists 190, 191, 192, 193 for forming the upper electrode on the upper electrode material 196. Further, the broken line portions show the over etched portions of the resists for forming the upper electrodes. Note if there are even intervals between the upper electrodes, such broken line portions may become portions of the resists for forming the upper electrodes.
After forming the upper electrodes, the ferroelectric layers and lower layers are formed in sequence. Because of this manufacturing sequence, the sizes of the upper electrodes are relatively smaller than those of the ferroelectric layers or lower electrodes. Namely, a redundant area for etching the ferroelectric layers or lower electrodes is needed, and thus positioning margins on the ferroelectric layers uncovered by the upper electrodes are provided. In addition, the sizes of the upper electrodes are formed smaller than those of the ferroelectric layers for preparing the redundant area without the upper electrode on the ferroelectric layers.
In addition, as discussed above, FIG. 36 illustrates a cross section of the line “S-T” in FIG. 35. FIG. 37 illustrates a memory block adjacent to the memory block in FIG. 36 including a block selecting transistor and memory cells of the cross sectional view of the line “U-V” and its extension in FIG. 35.
As shown in FIG. 37, a second block selecting transistor includes a fourth gate 130, a fifth impurity-diffused region 131, and a sixth impurity-diffused region 132 formed on the semiconductor substrate 103. Further, a third bit line contact wire 133 is connected to the fifth impurity-diffused region 131, and a second metal wire contact 134 is connected to the third bit line contact wire 133. A fourth bit line contact wire 135 is connected to the second metal wire contact 134, and a second bit line 136 is connected to the fourth bit line contact wire 135.
In addition, an isolation layer 137 is formed on the semiconductor substrate 103 and is adjacent to the sixth impurity-diffused region 132. A passing word line is formed on the isolation layer 137, and in which the passing word line is the first gate 100 of the block selecting transistor as shown in FIG. 36.
Also, a third cell transistor includes a seventh impurity-diffused region 138, a second gate 108 and an eighth impurity-diffused region 139 formed on the semiconductor substrate 103, and the seventh impurity-diffused region 138 is adjoined to the isolation layer 137.
A third capacitor includes a third lower electrode 140, a third ferroelectric layer 141 and a third upper electrode 142 formed over the eighth impurity-diffused region 139 and the second gate 108. The third lower electrode 140 is connected to the eighth impurity diffused region 139 by a third polysilicon plug 143.
In addition, a second contact plug 144 is connected to the seventh impurity-diffused region 138, and a second metal wiring 145 is connected to the second contact plug 144. A third metal contact 146 is also formed between the third upper electrode 142 and the second metal wiring 145 and is connected to them.
Note a fourth cell transistor includes the eighth impurity-diffused region 139, the third gate 118 and a ninth impurity-diffused region 147. Further, the third lower electrode 140 and the third ferroelectric layer 141 are formed over the third gate 118 and the eighth impurity diffused region 139. A fourth capacitor includes the third lower electrode 140, the third ferroelectric layer 141, and a fourth upper electrode 148 formed over the third gate 118.
Note a fourth memory cell includes a fourth cell transistor and a fourth capacitor.
The fourth upper electrode 148 is formed on the third ferroelectric layer 141 and over the third gate 118. Also, a fourth metal contact 149 is formed on the fourth upper electrode 148, and a third metal wiring 150 is formed on the fourth metal contact 149. A third contact plug 151 is formed on the sixth impurity diffused region 132 and is connected to the second metal wiring 145. Further, as described above, the third memory cell placed in the end portion of the memory block is connected to the second block selecting transistor.
In this structure shown in FIG. 37, the connection between the sixth impurity-diffused region 132 and the seventh impurity-diffused region 138 with the isolation layer 137 therebetween includes a second metal wiring 145 in the same level as the metal layer between the upper electrode and the impurity-diffused region, so another word line such as a multilevel word line has to be formed by using other layers of the second metal wiring 145 or the second bit line 136 formed on the second metal wiring 145. It is inconvenient to use three layers for connecting over the isolation layer, bit line and multilevel word line. That is, if more layers are used, the manufacturing process is becomes more complicated.
By using a Capacitor On Plug (COP) type structure, the area size is reduced in half compared to the offset type. However, the area of the block selecting transistor is increased. In addition, the connection between the sixth impurity-diffusion region 132 and the seventh impurity diffusion region 138 with the second metal wiring 145 may cause the area of the block selecting transistor to be determined by the density of the second metal wiring 145.
Thus, the memory cell area is mainly determined and increased by the distance between the second contact plug 144 and the third metal contact 146, the distance between the second contact plug 144 and the forth metal contact 149, or the distance between the second metal wiring 145 and the third metal wiring 150. In contrast, the distance between the second contact plug 144 and the second gate 108, or the distance between the second gate 108 and the far end point of the seventh impurity-diffused region 138 does not significantly affect the area of the memory cell.
Further, FIG. 38 shows an overview of the portion of the plate line area of two memory blocks and FIG. 39 shows a cross sectional view of the line “W-X” in FIG. 38. As shown in FIG. 39, the memory block includes a plurality of memory cells, and a fifth cell transistor on an end portion of the memory block includes a tenth impurity-diffused region 160, a fifth gate 161, and an eleventh impurity-diffused region 162 formed on the semiconductor substrate 103.
Further, a sixth cell transistor placed in the second end portion of the memory block includes the eleventh impurity-diffused region 162, a sixth gate 163, and a twelfth impurity-diffused region 164 on the semiconductor substrate 103. Also, a seventh cell transistor placed in a third end portion of the memory block includes the twelfth impurity-diffused region 164, a seventh gate 165 and a thirteenth impurity-diffused region 166.
In addition, a fifth metal contact 167 is connected to the tenth impurity-diffused region 160, and is also connected to a first plate line 168 arranged over the tenth impurity-diffused region 160. A second plate line 169 connected to the other memory block is arranged over the eleventh impurity-diffused region 162 and has the same position as the first plate line 168 in the vertical direction.
A fifth capacitor includes a fourth lower electrode 170, a fourth ferroelectric layer 171 and a fifth upper electrode 172 formed over the tenth impurity-diffused region 160. A sixth metal contact 173 is formed between the first plate line 168 and the fifth upper electrode 172. A fifth memory cell includes the fifth cell transistor and the fifth capacitor.
A sixth capacitor includes a fifth lower electrode 174 formed over the eleventh impurity-diffused region 162 and the sixth gate 163, a fifth ferroelectric layer 175 formed on the fifth lower electrode 174, and a sixth upper electrode 176 formed on the fifth ferroelectric layer 175 and over the sixth gate 163. The fifth lower electrode 174 is connected to the eleventh impurity-diffused region 162 by a fourth polysilicon plug 177.
A fifth metal contact 178 is connected to the twelfth impurity-diffused region 164, and a fourth metal wiring 179 is connected to the seventh metal contact 178. An eighth metal contact 180 is formed and connected between the sixth upper electrode 176 and the fourth metal wiring 179.
Note a sixth memory cell includes the sixth cell transistor and the sixth capacitor.
A seventh capacitor includes a sixth lower electrode 181 formed over the seventh gate 165 and the thirteenth impurity-diffused region 166, a sixth ferroelectric layer 182 formed on the sixth lower electrode 181, and a seventh upper electrode 183 formed on the sixth ferroelectric layer 182 and over the seventh gate 165. The sixth lower electrode 181 is connected to the thirteenth impurity-diffused region 166 by a fifth polysilicon plug 184, and a ninth metal contact 185 is formed and connected between the seventh upper electrode 183 and the fourth metal wiring 179.
A seventh memory cell includes a seventh cell transistor and a seventh capacitor.
In this structure, the distance “L” between the fifth upper electrode 172 and the sixth upper electrode 176 is larger than the distance “M” between the sixth upper electrode 176 and the seventh upper electrode 183. This difference is caused by the fifth upper electrode 172 being offset from the fifth gate 161 in a horizontal direction. The distance “M” is same as the distance between other memory capacitors respectively placed in an adjacent location in the same memory block.
Because of the micro loading effect, the fifth upper electrode 172 is formed smaller in size compared with the sixth upper electrode 176, the seventh upper electrode 183 and other upper electrodes in the same memory block. Because of the different size of the fifth upper electrode 172, the fifth capacitor may have deteriorated characteristics compared to other memory capacitors.
Further, a block selecting transistor in the block selecting section is provided in the end portion of the memory cell block. The capacitors are provided in an even interval in the memory cell block, except in the end portion of the memory cell block (where a capacitor is not provided). Therefore, in the end portion of the memory cell block, the periodicity of the memory cells is not maintained, and thus the distance between the capacitors is larger than that of capacitors in a normal area because of the length of the block selecting transistor.
Further, if the periodicity of the capacitors is not maintained, the characteristics of the capacitor in the end portions of the memory block may deteriorate. This deterioration is caused by a change of resist dimension for the change of the cross sectional shape of the upper electrode or lower electrode, or the increase of the distance between the capacitors by a micro loading effect during the fabricating process.
In addition, in the end portion of memory block which has relatively large opening area of resist, the amount of etching is larger than the amount of etching in other portions of memory cells.
Further, in the memory cell neighboring the plate line, the periodicity of the memory cell is not maintained. Therefore, the characteristic of the memory in the memory cell neighboring the plate line may also be damaged. In addition, a high density of memory cells may be reduced by using metal wiring for connecting the impurity-diffused regions.
The above deterioration of the memory capacitor adjacent to the block selecting transistor or plate line does not meet the demands for a more integrated and reliable semiconductor memory. Further, the above scale increase of memory cell occurs from using the first metal contact wire between the impurity-diffused regions with an isolation region between them and does not meet the demands for a more integrated and reliable semiconductor memory.